1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device with a built-in self test circuit (referred to as “BIST circuit” hereinafter).
2. Description of the Background Art
A semiconductor memory device includes a memory cell array with a plurality of memory cells. In accordance with microminiaturization of semiconductor memory devices, the size of each memory cell becomes smaller. The possibility is high of a defect being caused by dust and the like during the fabrication process. Also, the interference of data between adjacent cells cannot be ignored in accordance with the microminiaturization of the memories. It is therefore necessary to test the circuit including the memory cells prior to shipment of a semiconductor memory device as a product.
Conventionally, a memory tester (auto test equipment; referred to as “ATE” hereinafter) is used to test a semiconductor memory device. The ATE is an expensive apparatus.
An example of a conventional arrangement in such testing is shown in FIG. 1. Referring to FIG. 1, a memory 220 to be tested is connected to a tester 222. A clock signal is applied to memory 220 via a clock signal line 26 and a clock input pin 36. Input data and address signals are applied to memory 220 via an input line 28. The test result is read out from memory 220 via an input/output pin 40 and an input/output line 24.
Memory 220 includes a memory array 230, an input buffer 242, a control circuit 234, and an input/output circuit 232.
In a test operation, data to be written into a memory cell is applied to memory 220 from tester 222 via input/output lines 24 and input/output pins 40. Also, an address signal and a control signal are applied to control circuit 234 via input lines 28, input pins 38, and input buffers 242. Data is written into the specified address in memory array 230. That data is read out and applied to tester 222 via input/output buffer 248, input/output pins 40 and input/output lines 24. Tester 222 determines the test result.
In this conventional case, a total of nineteen input lines 28 is required when memory array 230 corresponds to 4 megawords×4 banks. More specifically, the nineteen input lines 28 correspond to 13 bits for the address signal, 2 bits for the bank address signal, and 4 bits for input/output control signals (/CS, /RAS, /CAS, /WE). Note that a forward slash “/” before a signal name indicates that the signal is low-active. Also, sixteen input/output lines 24 are required for one 16-bit word. It is to be noted that only four input/output lines 24 are required in the degeneration test that will be described afterwards.
The semiconductor memory device referred to as a DRAM (Dynamic Random Access Memory) has the capacity increased by virtue of development of the recent microminiaturization technique. Since the number of memory cells to be subjected to testing increases, the time required for testing will take longer if the above-described method is employed. Furthermore, it is necessary to carry out testing according to many test patterns since the data retained in the memory cell is influenced by its own value and the value of adjacent memory cells. The number of test patterns increases exponentially with the increase of the number of memory cells. Therefore, the time required for testing also increases significantly. In order to ensure an ATE that can accommodate a longer testing time, a large amount of investment in equipment was required to fabricate a semiconductor memory device.
Conventionally, testing was carried out from the standpoint of the user of the semiconductor memory device to allow a semiconductor memory device to be tested as simply as possible. For example, an ROM (read only memory) in which test patterns are stored is provided in a semiconductor memory device. In a testing operation, data is written into each memory cell according to the test pattern from this ROM to be compared with data that is read out and written (expected value). Testing was carried out in such a way.
Also, in order to reduce the test cost, the inputs/outputs (I/O) are degenerated in a wafer test to provide the same number of measure objects. Here, the meaning of “degeneration” is set forth in the following. The address of a memory cell in a memory cell array is specified for every sub word line. A plurality (for example 4) of subword lines are connected to one main word line. When a defect is found, repair is carried out in the unit of this main word line (replaced with spare cells). Therefore, testing is to be carried out in the unit of this main word line. This means that several bits of the lower order of the address are not required. This is called “degeneration”.
The recent semiconductor memory devices have a multi bank structure to read out data speedily. Readout is effected in an interleaving manner. In this readout, a plurality of bits identical in number to the inputs/outputs must be output from each bank. However, the number of inputs/outputs of the semiconductor memory device increases as a result of the increase of the number of bits that can be processed at one time by the computer or the like. As a result, the effect on data caused by interference between input/output data has increased. Therefore, the combination test of input/output data as the testing item is important. However, such testing is difficult with the above-described degeneration test.
The number of patterns estimated for the test pattern is increased in accordance with the microminiaturization and larger capacity of the semiconductor memory device. The capacity of the ROM in which these patterns are stored must also be increased. Thus, there was a problem that the required chip area becomes larger. Also, reduction in the charge margin of the stored data caused by microminiaturization may affect the stored data such as in the case where the ground potential is slightly shifted to the high (H) side. There may be some patterns that are to be particularly tested after the semiconductor memory device has been actually designed and produced. The case where an ROM is employed cannot cope with such a problem.
In view of the foregoing, a test that can be carried out more flexibly is desirable from the standpoint of the manufacturer of a semiconductor memory device. A more flexible test is expected to counterbalance the increase in overhead (for example, a larger chip area), if any, in the semiconductor memory device per se from the overall view of the cycle of designing, fabricating, testing and shipping a semiconductor memory device.